The present invention relates to a logic integrated circuit device, and more particularly a static induction transistor logic integrated circuit (SITL) which has low consumption power, and a fabricating method thereof.
An injection type SITL composed of a lateral bipolar transistor used as a load element (injector) and a vertical static induction transistor (SIT) used as a driving transistor, has an excellent characteristic, that is less power consumption and a small power-delay time product of some fJ/gate. However, further improvement of SITL in a low power operation is left to be made. The present invention will be described in conjunction with the structure of the conventional type of SITL shown in FIG. 1.
FIG. 1(a) illustrates a sectional structure of a so-called planar-gate type SITL and FIG. 1(b) illustrates an equivalent circuit diagram thereof. A lateral PNP bipolar junction transistor (BJT) T.sub.1 composed of a P.sup.+ injector region 15, a n.sup.- base region 13a and a collector region which also acts as a P.sup.+ gate region 14 of a SIT, operates as the load element or injector transistor, and a vertical SIT T.sub.2 composed of the P.sup.+ gate region 14, a n.sup.- channel region 13, a n.sup.+ source region 12 and a n.sup.+ drain region 11, operates as a driving transistor. Then, these two transistors are wired to form an inverter circuit similar to I.sup.2. In this case, the n.sup.+ source region 12 is formed in the same region as the base electrode region fo the lateral BJT T.sub.1. When a supplied d.c. voltage is applied through an emitter electrode 5 to the device, the effectiveness of the supplied current depends almost entirely upon a hole transport factor .alpha. of the lateral BJT T.sub.1.
The hole transported factor .alpha. is reduced mainly by the recombination of holes injected from the p+ injector region 15 in the n.sup.- regions 13a, 13b and the n.sup.+ source region 12, in the boundaries thereof, and in the surface of n.sup.- region 13a. Moreover, even if the holes reach the P.sup.+ gate region 14, the drivability or operation speed of the SIT is lowered because of an ineffective component of the gate current which does not serve to operate the SIT. The ineffective gate current is caused mainly by holes being injected into the n.sup.- region 13 being just under the p.sup.+ gate region 14.
In FIG. 2, another example of the conventional SITL is illustrated, which has a lateral MOS FET (or SIT) as a load. FIG. 2(a) illustrates a sectional view thereof and FIG. 2(b) illustrates an equivalent circuit diagram thereof. A lateral MOS.FET T.sub.1 is used as a load, which composed of a P.sup.+ injector region 15 acting as a source, a P.sup.+ gate region 14 acting as a drain, a gate metal electrode 6, an oxide film as a gate insulator and a n.sup.- region 13a. On the surface of the n.sup.- region 13a, the channel is formed during device operation. In this case, the amount of ineffective current will be reduced since the load T.sub.1 is a majority carrier device. However, as shown in FIG. 2(b), BJT T.sub.1b is also structurally involved so that almost all holes injected from the bottom portion of the P.sup.+ injector region 15 will contribute to an ineffective current. Furthermore, as illustrated in FIG. 1, the static current is always flowing as long as the voltage a power source is being applied even if the switching operation is stopped. As a result, ineffective current accounts for the most part of current consumption in the logic circuit that maintains a static state and seldom switches, such as in a logic circuit for an electronic watch. The example shown in FIG. 2 is also structurally the same.